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Dr. H. V. Ravish Aradhya

Professor and  HOD (I/C)

Educational Qualification

B.E (Electronics),

M.E(Electronics),

Ph. D (VLSI Design-Low power)

Experience

Teaching: 31 years

Area of Interest

VLSI Design and Embedded System

Email ID

ravisharadhya@rvce.edu.in

 

Date of Joining at RVCE : 09.10.1997

Subjects Handled : System Verilog for Design and Verification, CAD Tools for VLSI design, System On Chip design, Digital System Design using VERILOG,Advanced Microcontrollers and Interfacing,DSP Architecture and Algorithms Microprocessors and Interfacing, Advanced Microprocessors and Interfacing, Digital System Design using VHDL, Low Power VLSI Design

No. of Projects guided to UG Students :  80

No. of Projects guided to PG Students : 40

No. of Ph.D Guiding/Guided: 06/02

External Connect
1. Panel member for DPC/Review as subject expert at URSC [ISRO]
2. Academia Vice-chair DVCON-International conference

Publication Details

For recent journal and conference publications Click here

(i) International Journals: 49

  1. Ravish Aradhya H. V, Ashish Kapania, “Design Space Exploration of Power Efficient Cache Design Techniques,” Advances in Networks and Communications, Book-1, ISBN: 978-3-642-17878-8_37, SPRINGER Berlin Heidelberg, Jan-2011, pp. 362-371.

(Download link: https://link.springer.com/chapter/10.1007/978-3-642-17878-8_37)

  1. Ravish Aradhya H. V, B. V. Praveen Kumar, Dr. K. N Muralidhara, “Design of Low Power Arithmetic Unit (AU) based on Reversible Logic,” International Journal of VLSI and Signal Processing Applications (IJVSPA), Vol. 1, Issue 1, ISSN: 2231-3575, Apr-2011, pp. 30- 38.

(Download Link: http://www.sciencedirect.com/science/article/pii/S1877705812009186)

  1. Ravish Aradhya H. V, G Mithun Kumar, Dr. K. N Muralidhara, “Modelling of complex analog circuits with assertions and automatic processing of Waveforms,” International Journal of Advanced Engineering Sciences and Technologies (IJAEST), Vol. No. 6, Issue No. 2, pp. 220 – 223, ISSN: 2230-7818, May-2011.

  2. Ravish Aradhya H. V, G Mithun Kumar, Dr. K. N Muralidhara, “A Novel assertion based Methodology to verify mixed signal SOC designs in Digital and Mixed signal verification flow,” International Journal of Engineering Science and Technology (IJEST), ISSN: 0975–5462, Vol. No. 3, Issue No. 6, June 2011, pp. 4721-4727, June-2011.

  3. H V Ravish Aradhya, B. V. Praveen Kumar, Dr. K. N Muralidhara, “Design of Control unit for Low Power ALU Using Reversible Logic,” International Journal of Scientific and Engineering Research, France, Volume 2, Issue 7, ISSN 2229-5518, Sep-2011, pp. 01-07.

(Download Link: http://www.ijser.org/researchpaper%5CDesign-of-Control-unit-for-Low-Power-ALU-Using-Reversible-Logic.pdf)

  1. H V Ravish Aradhya, J. Lakshmesha, Dr. K. N Muralidhara, “Design Optimization of Reversible Logic Universal Barrel Shifter for Low Power Applications,” International Journal of Computer Applications, New York, USA, Volume 40, Issue 15, ISSN 0975-8887, Feb-2012, pp. 26-34. (Paper Reference ID: pxc3877379)

(Download Link: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.259.783&rep=rep1&type=pdf)

  1. H V Ravish Aradhya, G. Rekha, Dr. K. N Muralidhara, “Simulation and Synthesis of Combinational Shifter using Reversible Gates,” International Journal of Computer Applications, USA, Vol. 41, Issue 15, ISSN 0975-8887, Mar-2012, pp.26-35 (Paper Reference ID: pxc3879354).

(Download Link:

https://pdfs.semanticscholar.org/d114/1b0ebcac839372255b37a5496a12be791887.pdf)

  1. H V Ravish Aradhya, R. Chinmaye, Dr. K. N Muralidhara, “Design, Optimization and Synthesis of Efficient Reversible Logic Binary Decoder,” International Journal of Computer Applications (IJCA), New York, USA, ISSN- 0975-8887, Vol. 46, Issue. 6, May-2012, pp.45-51 (Paper Reference ID: pxc3879354).

(Download Link: http://research.ijcaonline.org/volume46/number6/pxc3879354.pdf)

  1. H V Ravish Aradhya, H. R. Madan, M. Girish Kumar, V. Ebenezer, “Considerations of FinFET Based 6T SRAM Cells,” International Journal of Science Research, Vol. 01, Issue 03, Dec-2012, pp. 134-136.

(Download Link: http://journal.tumkuruniversity.ac.in:8080/index.php/ijsr/article/view/68)

  1. H V Ravish Aradhya, H. R. Madan, M. Akshay Bhounsley, V. Ebenezer, “Comparative Study of DRAM for High & Low Power CMOS process technology,” International Journal of Science Research, Vol. 01, Issue 03, Dec-2012, pp. 137-138.

(Download Link: http://journal.tumkuruniversity.ac.in:8080/index.php/ijsr/article/view/69)

  1. H V Ravish Aradhya, H. R. Madan, M. Akshay Bhounsley, V. Ebenezer, “Comparative Study of SRAM & DRAM for various CMOS process technology,” International Journal of Science Research, Vol. 01, Issue 03, Dec-2012, pp. 141-143.

(Download Link: http://journal.tumkuruniversity.ac.in:8080/index.php/ijsr/article/view/72)

  1. H V Ravish Aradhya, H. R. Madan, Md. Luqman, K. Suresh, “Design and Performance Analysis of 8T SRAM for Different Scaled Technologies,” International Journal of Science Research, Vol. 01, Issue 03, Dec-2012, pp. 151-153.

(Download Link: http://journal.tumkuruniversity.ac.in:8080/index.php/ijsr/article/view/74)

  1. H V Ravish Aradhya, J. Lakshmesha, Dr. K. N Muralidhara, “Reduced Complexity Hybrid Ripple Carry Look Ahead Adder,” International Journal of Computer Applications (IJCA), New York, USA, ISSN- 0975-8887, Vol. 70, Issue. 28, May-2013, pp. 13-16. (Paper Reference ID: pxc388202).

(Download Link: http://research.ijcaonline.org/volume70/number28/pxc3888202.pdf)

  1. H V Ravish Aradhya, G. Rekha, Arun Kumar P. Chavan, “Bio-Inspired Motion Detector Model Simulated on Xilinx ISE,” International Journal of Computer Applications (IJCA), New York, USA, ISSN- 0975-8887, Vol. 72, Issue. 13, May-2013, pp.29-32. (Paper Reference ID: pxc388202)

(Download Link: http://research.ijcaonline.org/volume72/number13/pxc3889129.pdf)

  1. Dr. H V Ravish Aradhya, Srikant M. Pattar, “Novel Low Power and High Speed 8T-Full Adder,” International Journal of Scientific and Engineering Research (IJSER), France, ISSN: 2229-5518, Vol. 4, Issue. 8, Aug-2013, pp. 1156-1160. (Paper Reference ID: I027256)

(Download Link: http://www.ijser.org/researchpaper/Novel-Low-Power-and-High-Speed-8T-Full-Adder.pdf)

  1. Dr. H V Ravish Aradhya, et al, “Design and Optimization of Reversible carry look ahead Adder Circuit,” International Journal of Electronics and Communication Engineering (IJECE), ISSN: 2278-991X, Vol. 03, Issue.3, May-2014, pp. 65-72. Received “Best Paper” Award (Dated: 09th Dec 2014).

(Download Link: https://issuu.com/iaset/docs/7._electronics_-_ijece_-_design_and)

  1. Dr. H V Ravish Aradhya and Roopa H K, “Comparative study of Bluetooth Testing Automation Tools on Android,” International Journal of Scientific Engineering and Technology Research, ISSN: 2319-8885, Vol. 3, Issue.15, June-2014, pp. 3196-3198.

(Download Link: http://ijsetr.com/uploads/425316IJSETR1639-545.pdf)

  1. Dr. H V Ravish Aradhya, et al, “Design and Verification of Analog Phase Locked Loop Circuit,” International Journal of Combined Research and Development (IJCRD), ISSN: 2321-225X, Vol. 02, Issue.6, June-2014, pp. 01-05.

(Download Link: http://www.ijcrd.com/files/vol_2_issue_6/4627.pdf)

  1. Dr. H V Ravish Aradhya, Aravindkumar D Gumtaj, Mohana, Gouri S Katageri, “GPS and GSM Based Database Systems for User Access,” International Journal of Software and Web Sciences (IJSWS), ISSN: 2279-0071, Vol.1, Issue.12, March-May-2015, pp. 24-28. STEM Scientific Online Media and Publishing House, Georgia-31008, USA.

(Download Link: http://iasir.net/IJSWSpapers/IJSWS15-214.pdf)

  1. Dr. H V Ravish Aradhya, et al, “Design and Performance Comparison of finFET, CNFET and GNRFET based 6T SRAM,” International Journal of Science and Research (IJSR), ISSN: 2319-7064, Vol. 4, Issue. 04, Apr-2015, pp. 24-28.

(Download Link: https://www.ijsr.net/conf/NCKITE2015/162.pdf)

  1. Dr. H V Ravish Aradhya, B. V. Vishwas, “A Novel SRAM Cell Design for Low Power
    Applications,” International Journal of Engineering Research and Technology (IJERT), ISSN: 2278-0181, Vol. 04, Issue. 06, June-2015, pp. 1146-1149.

(Download Link: http://www.ijert.org/view-pdf/13570/a-novel-sram-cell-design-for-low-power-applications)

  1. Dr. H V Ravish Aradhya, et al, “GNRFET based 8-Bit ALU,” International Journal of Electronics and Communication Engineering (IJECE), ISSN: 2278-991X, Vol. 05, Issue. 01, Jan-2016, pp. 65-72. Impact Factor (JCC) - 2015:3.6986; Index Copernicus Value (ICV) - 2015:3.0; NAAS Rating: 3.06.

(Download Link: https://archive.org/details/4.IJECEGNRFETBASED8BITALU)

  1. Dr. H V Ravish Aradhya, Ranjit K G, Arunkumar P Chavan, “Design and Implementation of 8-bit ALU in Sub-Threshold Adiabatic Logic,” International Journal of Communication in Applied Electronics (IJCAE), July 2017, 973-93-80896-95-0,

  2. Ravish Aradhya H. V, Sachin M. Revannanavar, “Analysis, Physical Design and Power Optimization of Block Signal Estimator for High Speed Serial Interface,” International Journal of Science and Research (IJSR), ISSN (Online): 2319-7064, Index Copernicus Value (2015): 78.96 | Impact Factor (2015): 6.391, Aug 2017. Vol. 06, Issue. 08, pp. 916-920. (Download Link:  https://www.ijsr.net/archive/v6i8/ART20176029.pdf)

  3. Ravish Aradhya H. V, Manjunatha Rao V, “Clock Power Optimization in VLSI design at Advanced Technology Nodes,” International Journal of Computer Applications (IJCA), ISSN: 0975 – 8887, Vol. 169, Issue. 09, July 2017, pp. 29-34.

(Download Link:  www.ijcaonline.org/archives/volume169/number9/rao-2017-ijca-914880.pdf)

  1. Ravish Aradhya H. V, Apoorva Raghunandan, “Performance Analysis of Advanced Adders Under Changing Technologies,” International Journal of Innovations in Engineering and Technology (IJIET), Vol. 12, Issue 2, January 2019, ISSN: 2319-1058, pp. 87-94. (Download Link:  http://ijiet.com/wp-content/uploads/2019/02/15.pdf)

  2. Ravish Aradhya H. V, Shreyas H S, Arunkumar P Chavan, “Design and Analysis of Low Power VCO Enabled Quantizer for CT Sigma Delta ADC,” Indian Journal of Public Health Research & Development (IJPHRD), Vol. 10, Issue 5, Jun 2019, ISSN: 0976-0245, E-ISSN:0976-5506, pp. 921-927. (Download link: http://www.indianjournals.com/ijor.aspx?target=ijor:ijphrd&volume=10&issue=5&article=174)

  3. Ravish Aradhya H. V, Nehal B, “Design of Field Area Network on Advanced Metering Infrastructure,” International Journal of Emerging Technologies and Innovative Research (JETIR), Vol. 12, Issue 2, January 2019, ISSN: 2349-5162, pp. 87-94.

  4. Ravish Aradhya H. V, Bharath B. Shetty, “User Service REST API using Spring Boot,” International Journal of Computer Sciences and Engineering (IJCSE), Vol. 12, Issue 2, May 2019, ISSN: 2347-2697, pp. 87-94.

  5. Ravish Aradhya H. V, Gagan A, “Logic Structure Reduction Scheme for FINFET based TSPC Flip-Flop,” International Journal of Engineering Research and Technology (IJERT), Vol. 8, Issue 6, Jun 2019, ISSN: 2278-0181, pp. 431-435. (Download link: https://www.ijert.org/research/logic-structure-reduction-scheme-for-finfet-based-tspc-flip-flop-IJERTV8IS060349.pdf)

  6. Ravish Aradhya H. V, Mohana, “Object Detection and Classification Algorithms using Deep Learning for Video Surveillance Applications,” International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue 8, Jun 2019, ISSN: 2278-3075, pp. 386-395. (Scopus Indexed) [Download link: https://www.ijitee.org/wp-content/uploads/papers/v8i8/H6362068819.pdf

(ii) International Conferences: 85

  1. H. V. Ravish Aradhya, Prasad P. Kamat, Dr. K. N. Muralidhara, “Multi Core ALU – a low power approach,” in the proceedings of International Conference on Computer, Communication and Instrumentation (3CI-07); RVCE, Bangalore-59, India, 23-25 Nov, 2007.

  2. H. V. Ravish Aradhya, V. Swetha, Dr. K. N. Muralidhara, “Practical Aspects Power Verification & Automation,” in the proceedings of International Conference on Sensors, security, software& Intelligent systems (ISSSIS-09), CIT, Coimbatore, India, 08-10, Jan 2009.

  3. H. V. Ravish Aradhya, Mahesh K, Dr. K. N. Muralidhara, “Design and Implementation of an Advanced External Interrupt Controller Unit [AEICU] on Cortex-R4 Processor,” in the proceedings of International Conference on System Dynamics and Control (ICSDC-10); MIT, Manipal, India, 19-22, Aug-2010.

  4. H. V. Ravish Aradhya, B. V. Praveen Kumar, Dr. K. N. Muralidhara, “Design of Control unit for Low Power AU Using Reversible Logic,” in the proceedings ELSEVIER- International Conference on Communication technology and System design (ICCTSD-2011), AIT, Coimbatore, India., Dec 07-09, 2011.

(Download Link: https://www.sciencedirect.com/science/article/pii/S1877705812009186)

  1. H. V. Ravish Aradhya, R. Chinmaye, Dr. K. N. Muralidhara, “Design, Optimization and Synthesis of Efficient Reversible Logic Binary Encoder,” in the proceedings of International Conference on Recent Trends in Computer Science and Engineering (ICRTCSE-2012), Apollo College of Engineering, Kanchipuram, TN, India, 07-09, Apr-2012.

  2. Ravish Aradhya H. V, G. Malleswara Rao, Dr. K. N. Muralidhara, “FPGA Implementation of IEEE-754, Single Precision Floating Point Arithmetic,” in the proceedings of International Conference on Recent Trends in Computer Science and Engineering (ICRTCSE-2012), Apollo College of Engineering, Kanchipuram, TN, India, 07-09, Apr-2012.

  3. Ravish Aradhya H. V, G. Rekha, Arun Kumar P. Chavan, “VLSI implementation of Bio-Inspired Motion Detector model,” in the proceedings of International Conference on Information & Communication Engineering (ICICE-2013), ISBN: 978-81-31703-83-2, June-2013, Bangalore, India, pp. 45-50.

  4. Ravish Aradhya H. V, Mohana, R. Chethan, R. Shridhar, “Optical Character Recognition to Speech Conversion,” in the proceedings of ELSEVIER - 2nd International Conference on Emerging Research in Computing, Information, Communication and Applications (ERCICA-2014), Nitte Meenakshi Institute of Technology, Bangalore, Karnataka, India, 01-02 Aug-2014. Elsevier Science and Technology Publications, ISBN: 9789351072607, pp: 132-136.

  5. Ravish Aradhya H. V, Mohana, Kiran Anil Chikodi, “Real Time Objects Detection and Positioning in Multiple Regions Using Single Fixed Camera View for Video Surveillance Applications,” in the proceedings of IEEE - International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO-2015), 24-25 Jan 2015, Vignan's Institute of Information Technology, Duvvada, Visakhapatnam, AP, India. IEEE Explorer: 978-1-4799-7678-2/15/$31.00, ©2015 IEEE, (Conference Record Number: #35593), pp:1631-1636

(Download Link: http://ieeexplore.ieee.org/document/7253654/)

  1. Ravish Aradhya H. V, Mohana, Nikhil Raju Shalgar, “Design of Square Spiral Nano-Antenna in Infra-red Region for Solar Energy Harvesting,” in the proceedings of IEEE - International Conference on Engineering and Technology (ICETECH-2015), 20 Mar 2015, Rathinam Institute of Technology, Coimbatore, Tamilnadu, India. IEEE: 978-1-4799-7678-2/15/$31.00, ©2015 IEEE, (Conference Record Number: #35961), 20th March 2015, pp: 1026-1031. Received “Best Paper” Award (Dated: 20th Mar 2015).

  2. Ravish Aradhya H. V, Mohana, R. Chethan, “Correlator Based Group Delay Measurement for Delta-DOR Signals,” in the proceedings of IEEE - Global Conference on Communication Technologies (GCCT-2015), Noorul Islam University, Kanyakumari district, Tamil Nadu, India. IEEE Explorer: 978-1-4799-8553-1/15/$31.00 ©2015 IEEE, (Conference Record Number: #35855), pp: 419-422.

  3. Ravish Aradhya H. V, Mohana, R. Sagar, “Remote Monitoring of Heart Rate and Music to Tune the Heart Rate,” in the proceedings of IEEE - Global Conference on Communication Technologies (GCCT-2015), Noorul Islam University, Kanyakumari district, Tamil Nadu, India. IEEE Explorer: 978-1-4799-8553-1/15/$31.00 ©2015 IEEE, (Conference Record Number: #35855), pp: 678-681.

  4. Ravish Aradhya H. V, Mohana, Kiran Anil Chikodi, “Real Time Object Counting and Classification for Video Surveillance Applications from single fixed camera,” in the proceedings of 2nd SPRINGER - International Conference on Networking, Information & Communication (ICNIC-2015), 18-20 May 2015, Sri Venkateshwara College of Engineering, Bengaluru, Karnataka, India, pp:1-6.

  5. Ravish Aradhya H. V, Mohana, G. S. Pallavi, “CAP - Ro Translator for UMTS to LTE Protocol Conversion,” in the proceedings of 2nd SPRINGER - International Conference on Networking, Information & Communication (ICNIC-2015), 18-20 May 2015, Sri Venkateshwara College of Engineering, Bengaluru, Karnataka, India, pp:1-4.

  6. Ravish Aradhya H. V, Aravindkumar D. Gumtaj, Mohana, “Real Time Smart, Intelligent and Novel Embedded Vehicle Interceptor for Security Applications,” in the proceedings of 3rd SPRINGER - International Conference on “Emerging Research in Computing, Information, Communication and Applications (ERCICA-2015), 31st July – August 1st 2015 at NMIT Bangalore, India, pp-521-534. ISBN978-81-322-2553-9

(Download Link: https://link.springer.com/chapter/10.1007%2F978-81-322-2553-9_47)

  1. Ravish Aradhya H. V, Mohana, G. S. Pallavi, “CAP to Diameter Protocol Converter,” in the proceedings of IEEE - International Conference on Green Computing and Internet of Things (ICGCIOT-2015), 08-10 Oct 2015, Galgotias College of Engineering and Technology, Greater Noida, New Delhi, India, pp-598-602. [978-1-4673-7910-6/15/$31.00 ©20 15 IEEE]

(Download Link: http://ieeexplore.ieee.org/document/7380535/)

  1. Ravish Aradhya H. V, Mohana, Sagar R, “Correlator Based Group Delay Measurement for Delta - DOR Signals,” in the Proceedings of IEEE - Global Conference on Communication Technologies (GCCT 2015), 08-10 Mar 2015, College of Engineering and Technology, Kanyakumari, Tamilnadu, India, pp:419-422. [978-1-4799-8553-1/15/$31.00 © 2015 IEEE]

(Download Link: http://ieeexplore.ieee.org/document/7342697/)

  1. Ravish Aradhya H. V, Mohana, Sagar R, “Remote Monitoring of Heart Rate and Music to Tune the Heart Rate,” in the Proceedings of IEEE - Global Conference on Communication Technologies (GCCT 2015), 08-10 Mar 2015, College of Engineering and Technology, Kanyakumari, Tamilnadu, India, pp:678-681. [978-1-4799-8553-1/15/$31.00 © 2015 IEEE]

(Download Link: http://ieeexplore.ieee.org/document/7342748/)

  1. Ravish Aradhya H. V and Karnati Gopi Manohar, “Multiple Valued Logic (MVL) Based Combinational Building Blocks,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT-­2016), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 20-21 May 2016. Pp: 2088-2092, [978-1-5090-0774-5/16/$31.00 © 2016 IEEE].

(Download Link: http://ieeexplore.ieee.org/document/7808207/)

  1. Ravish Aradhya H. V, et al, “Design, Analysis and Performance comparison of GNRFET based Adiabatic 8-Bit ALU,” in the proceedings of IEEE - International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT-­2016), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 20-21 May 2016. Pp: 1584-1588, [978-1-5090-0774-5/16/$31.00 © 2016 IEEE] Ravish Aradhya  H  V,   Madan  H  R,   Suraj  M  S,   Megaraj  T  Mahadikar, Muniraj R  and  Mohammed  Moiz),

(Download Link: http://ieeexplore.ieee.org/document/7808099/)

  1. Ravish Aradhya H. V, et al, “Real-Time Implementation of Object Detection and Tracking on DSP for Video Surveillance Applications,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2016), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 20-21 May 2016. (Ravish Aradhya  H  V,   Suraj  M, Suraj S, Prasad Dongrekar, Srikanth Sajjanar and Mohana), pp: 1965-1969, [978-1-5090-0774-5/16/$31.00 © 2016 IEEE]

(Download Link: http://ieeexplore.ieee.org/document/7808180/)

  1. Ravish Aradhya H. V, et al, “Design, Analysis and Performance comparison of GNRFET based 8-Bit ALUs,” in the proceedings of IEEE - International conference on Recent Advances in Integrated Navigation Systems (RAINS-­2016), R. L. Jalappa Institute of Technology, Doddaballapur, Bengaluru, 6-7 May 2016. (Ravish Aradhya  H  V,   Madan  H  R,   Suraj  M  S,   Megaraj  T  Mahadikar, Muniraj  R  and  Mohammed  Moiz)

(Download Link: http://ieeexplore.ieee.org/document/7764366/)

  1. Ravish Aradhya H. V, Smitha G. S, “mGDI Based Parallel Adder For Low Power Applications,” in the proceedings of 3rd Springer - International Conference on ‘Microelectronics Circuits and Systems’ (MICRO-2016), 9-10th July 2016, pp. 26-31, Science City, Kolkata, India. (Organizer: Forum of CCSN).

(Download Link: https://link.springer.com/article/10.1007/s00542-017-3438-1

Or https://link.springer.com/content/pdf/10.1007/s00542-017-3438-1.pdf)

[SCI : Springer-Microsystem Technologies, ISSN: 0946-7076 (Print) 1432-1858 (Online)]

  1. Ravish Aradhya H. V, et al, “Implementation of Real Time Moving Object Detection and Tracking on FPGA for Video Surveillance Applications,” in the proceedings of IEEE - International conference on Distributed Computing, VLSI, Electrical Circuits, and Robotics (DISCOVER­-2016), National Institute of Technology (NITK), Surathkal, Karnataka, 13-14 August 2016. (Ravish Aradhya H V, Suraj  M, Suraj S, Prasad Dongrekar, Srikanth Sajjanar and Mohana)

(Download Link: http://ieeexplore.ieee.org/document/7806248/)

  1. Ravish Aradhya H. V, et al, “Design and Performance comparison of Adiabatic 8-Bit Multipliers,” in the proceedings of IEEE - International conference on Distributed Computing, VLSI, Electrical Circuits, and Robotics (DISCOVER­-2016), National Institute of Technology (NITK), Surathkal, Karnataka, 13-14 August 2016. (Ravish  Aradhya  H  V,   Madan  H  R,   Suraj  M  S,   Megaraj  T  Mahadikar,

Muniraj  R  and  Mohammed  Moiz)

(Download Link: http://ieeexplore.ieee.org/document/7806237/)

  1. Ravish Aradhya H. V, Suraj K Mankani, Shreekant Sajjanar, Mohana, “Power and Area Optimization of Decimation Filter for Application in Sigma Delta ADC,” in the Proceedings of IEEE - International Conference on Circuits, Control, Communication and Computing (I4C-2016), 4-6 October 2016, M. S. Ramaiah Institute of Technology, Bangalore, India.

(Download Link: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8053268)

  1. Guruprasad, Mohana, Ravish Aradhya H. V, “PAPR Reduction and Performance Analysis of Modulation Techniques in OFDM for WLAN Applications,” in the Proceedings of IEEE - International Conference on Signal Processing, Communication, Power & Embedded System (SCOPES-2016), 3-5 October 2016, Centurion University, Odisa, India.

(Download Link: ieeexplore.ieee.org/document/7955703/)

  1. Mohana, Ravish Aradhya H. V, “Elegant and Efficient Algorithms for Real Time Object Detection, Counting, and Classification for Video Surveillance Applications from Single Fixed Camera,” in the Proceedings of IEEE-International Conference on Circuits, Control, Communication and Computing (I4C-2016), pp.220-226, 4-6 October 2016, M. S Ramaiah Institute of Technology, Bangalore, India. 

 (Download Link:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8053292)

  1. Mohana, Ravish Aradhya H. V, “Real Time Implementation of Emotion Detection and Classification system for Autism Patients,” in the Proceedings of IEEE - International Conference on Advance Computing and Software Engineering (ICACSE-2016), 14-15 October 2016, Kamla Nehru Institute of Technology, Sultanpur, Uttara Pradesh, India.

  2. Md. Musharaf Uddin Quraishi, Mohana, H.V. Ravish Aradhya, “Design of Skin Detection Algorithm Tool for Analysis of Real Time and Non-real Time Images using MATLAB,” in the Proceedings of IEEE - International Conference on Advance Computing and Software Engineering (ICACSE-2016), 14-15 October 2016, Kamla Nehru Institute of Technology, Sultanpur, Uttara Pradesh, India.

  3. Mohana, Ravish Aradhya H. V, “Elegant and Efficient Algorithms for Real Time Implementation of Object Detection, Classification, Tracking and Counting using FPGA Zynq XC7Z020 for Automated Video Surveillance Applications,” 10th IEEE Advanced Networks and Telecommunications Systems (ANTS-2016), 6-9 November 2016, J. N. Tata Auditorium, Indian Institute of Science (IISc), Bangalore, India.

(PhD Forum - Only presentation, this work will not be published)

  1. Ravish Aradhya H. V, Vidya P. K, Mohana, “Implementation of Highly Efficient Sorting Algorithm for Median Filtering using FPGA Spartan 6,” in the proceedings of IEEE - International Conference on ‘Innovative Mechanisms for Industry Applications’ (ICIMIA-2017), 21-23 Feb 2017, pp. 265-269, Dayananda Sagar College of Engineering, Bengaluru, India. ISBN: 978-1-5090-5960-7/17/$-31.00©2017, Received “Best Paper” Award (Dated: 23rd Feb 2017).

  (Download Link:  ieeexplore.ieee.org/document/7975614/)

  1. Ravish Aradhya H. V, et al, “Design and Implementation of Low power Mitchell Algorithm based Logarithmic Multiplier,” in the proceedings of IEEE - International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2017), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 19-20 May 2017. pp. 1389-1393, ISBN: 978-1-5090-3704-9/17/$31.00 © 2017 IEEE. (Ravish  Aradhya  H  V,   Ranjitha H V, and Pooja K S)

(Download Link:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8256828) pp.1402 - 1406

  1. Ravish Aradhya H. V, et al, “Sub-threshold Adiabatic Logic (SAL) Based Building Blocks for Combinational System Design,” in the proceedings of IEEE - International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2017), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 19-20 May 2017. pp. 96-100, ISBN: 978-1-5090-3704-9/17/$31.00 © 2017 IEEE. (Ravish  Aradhya  H.  V,   Ranjit K. G and Arun Kumar P. Chavan)

(Download Link:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8256565) pp. 96-100

  1. Ravish Aradhya H. V, et al, “Single Bit-line Low Power 9T Static Random Access Memory,” in the proceedings of IEEE - International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2017), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 19-20 May 2017. pp. 1914-1917, ISBN: 978-1-5090-3704-9/17/$31.00 © 2017 IEEE. (Ravish  Aradhya  H  V,   Akshatha P Inamdar and Divya P A)

(Download Link:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8256937) pp. 1943-1947

  1. Ravish Aradhya H. V, et al, “An Area efficient FPGA Implementation of Moving Object Detection and Face Detection using Adaptive Threshold method,” in the proceedings of IEEE - International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2017), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 19-20 May 2017. pp. 1589-1594, ISBN: 978-1-5090-3704-9/17/$31.00 © 2017 IEEE. (Ravish  Aradhya  H  V,   Vidya P Korakoppa and Mohana)

(Download Link:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8256870) pp. 1606-1611

  1. Ravish Aradhya H. V, et al, “Design and Analysis of Compact Printed Circuit Antenna for wireless Medical Telemetry Service,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2017), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 19-20 May 2017. pp. 1139-1142, ISBN: 978-1-5090-3704-9/17/$31.00 © 2017 IEEE. (Ravish Aradhya H V, Vijayashanth D, Vijith Venugopalan and Mohana)

(Download Link:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8256776) pp. 1139-1142
 

  1. Ravish Aradhya H. V, N Sameeksha Rai, Arun Kumar P. Chavan, “Design and implementation of 16 tap FIR filter for DSP Applications,” in the proceedings of IEEE – 2nd International Conference on Advances in Electronics, Computers and Communications (ICAECC 2018), 09-10 Feb 2018, REVA University, Karnataka, India.

  2. Apoorva Raghunandan, Mohana Mohana, Pakala Raghav and H.V. Ravish Aradhya, “Object Detection Algorithms for Video Surveillance Applications,” in the proceedings of IEEE - 7th International Conference on Communication and Signal Processing (ICCSP 2018), 03-05 April 2018, Melmaruvathur, TN, India.

  3. Akshay Mangawati, Mohana, Mohammed Leesan, H. V. Ravish Aradhya, “Object Tracking Algorithms for Video Surveillance Applications,” in the proceedings of IEEE - 7th International Conference on Communication and Signal Processing (ICCSP 2018), 03-05 April 2018, Melmaruvathur, TN, India.

  4. Akshatha P. Inmdar, Syed Shadab and H.V. Ravish Aradhya, “Optimization of Test Register Access Time for Next Generation SoCs,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2018), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 18-19 May 2018. pp. 1139-1142, ISBN: 978-1-5386-2440-1/18/$31.00 © 2018 IEEE.

  5. Vaishnavi Kumbargeri, Anusha Mahale and Dr. H V Ravish Aradhya, “Low power Logarithmic multiplier using FinFETs,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2018), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 18-19 May 2018. pp. 1139-1142, ISBN: 978-1-5386-2440-1/18/$31.00 © 2018 IEEE.

  6. Akshatha Inamdar, Ravish Aradhya H V, “Low Power Single Bit-line Power-gated SRAM,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2018), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 18-19 May 2018. pp. 1139-1142, ISBN: 978-1-5386-2440-1/18/$31.00 © 2018 IEEE.

  7. Pooja K S, Ravish Aradhya H V, “Design and Implementation of Low Power 6:3 Fast Counter based on Symmetric Stacking,” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2018), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 18-19 May 2018. pp. 1139-1142, ISBN: 978-1-5386-2440-1/18/$31.00 © 2018 IEEE.

  8. Pooja K S, Sundar Krishnakumar and Ravish Aradhya H V, “Verification of Interconnection IP for Automobile Applications using SystemVerilog and UVM” in the proceedings of IEEE -International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2018), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 18-19 May 2018. pp. 1139-1142, ISBN: 978-1-5386-2440-1/18/$31.00 © 2018 IEEE.

  9. Vaishnavi Kumbargeri, and Ravish Aradhya H V, “Design and Implementation of Logarithmic Multiplier Using FinFETs for Low Power Applications,” in the proceedings of Springer-3rd International Conference on Advanced Trends in Computer Science & Information Technology (ICERECT-18), 24-25 Aug, PES College of Engineering, Mandya, Karnataka, pp 895-902. Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 545)

(Download link: https://link.springer.com/chapter/10.1007/978-981-13-5802-9_78)

  1. Shreyas H S, Arunkumar P C and Ravish Aradhya H V, “Design and Analysis of Low Power VCO Enabled Quantizer for CT Sigma Delta ADC,” in the proceedings of International Conference on Advanced Trends in Computer Science & Information Technology (ICATCSIT-18), 24-25 Aug, Geethanjali Institute of Science and Technology, Nellur, AP. (Scopus Indexed)

  2. Mohana and Ravish Aradhya H V, “Simulation of Object Detection Algorithms for Video Survillance Applications,” in the proceedings of IEEE – 2nd International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud (I_SMAC­-2018), SCAD Institute of Technology, Palladam, Coimbatore, TN, India, 30 - 31 Aug 2018. 

  3. M T Ganesh Kumar, Sandeep Malik, Madan H R and Ravish Aradhya H V, “Design and performance analysis of 8-bit Modified Booth Multiplier,” in the proceedings of IEEE – 3rd International conference on Electrical Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT-2018), GSSS Institute of Engineering and Technology, Mysuru, Karnataka, India, 14 - 15 Dec 2018

  4. Ravish Aradhya H. V, Apoorva Raghunandan, “Area and Timing Analysis of Advanced Adders under changing Technologies,” in the proceedings of IEEE – 4TH International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2019), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 17-18 May 2019. pp. 1139-1142, ISBN: 978-1-7281-0630-4/19/$31.00 © 2019 IEEE.

  5. Ravish Aradhya H. V, Mohd Leesan U A, “Design of a Sequential Circuit Based on Multi-Threshold FinFET Technique,” in the proceedings of IEEE – 4TH International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2019), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 17-18 May 2019. pp. 1139-1142, ISBN: 978-1-7281-0630-4/19/$31.00 © 2019 IEEE.

  6. Ravish Aradhya H. V, Ganesh Kumar M T, Madan H R, Sandeep Malik, “Design and performance analysis of 8-bit Modified Wallace Tree Multiplier,” in the proceedings of IEEE – 4TH International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2019), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 17-18 May 2019. pp. 1139-1142, ISBN: 978-1-7281-0630-4/19/$31.00 © 2019 IEEE.

  7. Ravish Aradhya H. V, Arun Arahunashi, Neetu S, “Performance Analysis of Various SDN Controllers In Mininet Emulator,” in the proceedings of IEEE – 4TH International conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT­-2019), Sri Venkateshwara College of Engineering, Bengaluru – 562 157, 17-18 May 2019. pp. 1139-1142, ISBN: 978-1-7281-0630-4/19/$31.00 © 2019 IEEE.

  8. Ravish Aradhya H. V, Mohd Leesan Ul Aktab, Furqan Saberi, “Development of a Random Test Generator for Multi-Core Processor Design Verification,” in the proceedings of IEEE – 4TH International conference on Communication and Electronics Systems (ICCES­-2019), PPG Institute of Technology, Coimbatore, India, 17-19 July 2019, pp. 1139-1142, ISBN: 978-1-7281-0630-4/19/$31.00 © 2019 IEEE.

  9. Mohana, Ravish Aradhya H. V, “Design of Efficient Algorithms for Video Surveillance Applications using Artificial Intelligence,” 25th IEEE Advanced Computing and Communications Conference (ADCOM 2019), 5-7 September 2019, at International Institute of Information Technology (IIIT-B), Bangalore, India. (PhD Forum - Only presentation, this work will not be published)

(iii) National Journals: NIL

(iv) National Conferences: 24

  1. H. V. Ravish Aradhya, V. Swetha, Dr. K. N. Muralidhara, “Practical aspects of FEV using Cadence LEC,” in the proceedings of National level technical paper meet (NLTPM-08), Sambhram Institute of technology, Bangalore-97 during 04-05 Apr-2008.

  2. H. V. Ravish Aradhya, U. Jeevan Kumar, Dr. K. N. Muralidhara, “CAD tool for computing iteration bound of DSP chips," in the proceedings of National conference on Information Technology (NCIT-09) Bangalore Institute of technology, Bangalore-01, INDIA, March 2009.

  3. H. V. Ravish Aradhya, S. Sunitha, Dr. K. N. Muralidhara, “Square FIFO for data transfer between unrelated clock domains,” in the proceedings of National conference on recent trends in soft computing (NCRTSC-09), New Horizon CE, Bangalore-87 during 24-25 Apr-2009.

  4. H. V. Ravish Aradhya, G. Sunil Kumar Reddy, Dr. K. N. Muralidhara, “ASIC Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm,” in the proceedings of National conference on Recent Trends in Communication, Electronics and Information Technology(NCRTCEIT-09), CMRIT, Bangalore-37 during 14-15 May-2009.

  5. H. V. Ravish Aradhya, S. Sunitha, Dr. K. N. Muralidhara, “Practical Aspects of Boundary Scan and applications beyond interconnect test,” in the proceedings of National conference on recent trends in communication, electronics and information technology (NCRTCEIT-09), CMRIT, Bangalore-37 during 14-15 May-2009.

  6. H V Ravish Aradhya, G. Sunil Kumar Reddy, Dr. K. N. Muralidhara, “Design and Implementation of an optimized systolic array architecture for FSBMA for real time applications," in the proceedings of National conference on recent trends in communication, electronics and information technology (NCRTCEIT-09), CMRIT, Bangalore-37 during 14-15 May-2009.

  7. H. V. Ravish Aradhya, U. Jeevan Kumar, Dr. K. N. Muralidhara, “Estimation of Iteration Bound For DSP Algorithms Using LPM Method,” in the proceedings of National conference on VLSI and Multimedia communication (NCVM-09), RVCE, Bangalore-59 during 23-24 Oct-2009.

  8. H. V. Ravish Aradhya, K. Mahesh, Dr. K. N. Muralidhara, “Design and implementation of an advanced external interrupt controller unit [AEICU] on cortex-r4 processor,” in the proceedings of National Level Conference on Computers, Communication and Controls (N4C-11), R. V. College of Engineering, Bangalore, during 29-30 Apr-2010.

  9. H. V. Ravish Aradhya, C. Rohith Kumar, Dr. K. N. Muralidhara, “Design and implementation of Wireless fire surveillance system,” in the proceedings of National Level Conference on Computers, Communication and Controls (N4C-11), R. V. College of Engineering, Bangalore, during 29-30 Apr-2010.

  10. H. V. Ravish Aradhya, V. Sandeep, Dr. K. N. Muralidhara, “SPI Interface and Physical Layer of Low Energy Bluetooth,” in the proceedings of National Level Conference on Computers, Communication and Controls (N4C-11), R. V. College of Engineering, Bangalore, during 29-30 Apr-2010.

  11. H. V. Ravish Aradhya, V. Sandeep, Dr. K. N. Muralidhara, “Low Energy Bluetooth: An Evolution in Short Range Wireless Communication,” in the proceedings of National Level Technical Symposium TECHNISIUM’11, Siddaganga Institute of Technology (SIT), Tumkur, during 09-10 Apr-2011.

  12. H. V. Ravish Aradhya, H. R. Madan, Dr. K. N. Muralidhara, “CMOS Realization of Reversible BCD Adder,” in the proceedings of National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.

  13. H. V. Ravish Aradhya, H. R. Madan, Dr. K. N. Muralidhara, “CMOS implementation of reversible comparators,” in the proceedings of National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.

  14. H. V. Ravish Aradhya, H. R. Madan, Dr. K. N. Muralidhara, “Design and Performance Analysis of 6T-SRAM for Different Scaled Technologies,” in the proceedings of National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.

  15. H. V. Ravish Aradhya, H. R. Madan, Dr. K. N. Muralidhara, “Comparative Study of logic circuits based on MOSFET and FinFET under 32 nm process technology,” in the proceedings of National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.

  16. H. V. Ravish Aradhya, H. R. Madan, Dr. K. N. Muralidhara, “Comparative Study of DRAM for various CMOS process technology,” in the proceedings of National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.

  17. H. V. Ravish Aradhya, R. Chinmaye, Dr. K. N. Muralidhara, “Design and Optimization of Reversible Logic Decoder For Low Power Applications,” National conference on advanced VLSI and embedded technology (NCAVET-2012), New Delhi, during 28-29, Feb-2012.

  18. Dr. H V Ravish Aradhya, et al, “Design and Performance Comparison of finFET, CNFET and GNRFET based 6T SRAM,” in the proceedings of National Conference on Knowledge, Innovation in Technology and Engineering (NCKITE), Kruti Institute of Technology and Engineering, Raipur, 10-11 Apr-2015, pp. 24-28.

  19. Dr. H V Ravish Aradhya, et al, “Design and Performance Analysis of Low-Power Hybrid CMOS Full Adder Cells,” in the proceedings of National Conference on “ICT-Innovations for sustainability,” R. V. College of Engineering, Bengaluru, 16-17 May-2015.

  20. Ravish Aradhya H. V and Karnati Gopi Manohar, “Realization of universal gates of Multiple Valued Logic (MVL) using CMOS technology,” National conference on "Engineering, Technology and Management, 22-23 April 2016, R. V. College of Engineering, Bengaluru 560059.

  21. Ravish Aradhya H. V and Smitha G. S, “De-skew model for High speed Source synchronous SerDes PHY,” National conference on "Engineering, Technology and Management, 22-23 April 2016, R. V. College of Engineering, Bengaluru 560059

  22. Ravish Aradhya H. V and Pooja K S, “Verification of Peripheral Interconnect IP using SystemVerilog and UVM,” National conference on "Engineering, Technology and Management, 22-23 April 2018, R. V. College of Engineering, Bengaluru 560059

  23. Ravish Aradhya H. V and Akshatha P. Inamdar, “Verification of Peripheral Interconnect IP using SystemVerilog and UVM,” National conference on "Engineering, Technology and Management, 22-23 April 2018, R. V. College of Engineering, Bengaluru 560059

Books: Books Published/Adapted/Reviewed:

  1. Dr. Ravish Aradhya H. V., “Digital Integrated Circuits - A Comprehensive Approach for System Design and Analysis,” 1st Edition, Oxford University Press (India) 2015, ISBN: (In progress).

  2. Dr. Ravish Aradhya H. V., “Linear ICs-A System Design Perspective,” 1st Edition, Oxford University Press (India) 2015, ISBN: (In progress).

  3. Reviewed Gate-2014 material, Pearson Education (I) Pvt. Ltd., July-2014.

  4. Ravish Aradhya H. V., “Basic Electronics,” 1st Edition, McGraw-Hill (India) 2013, ISBN-13: 978-0-07-133310-8.

  5. Moris M. Mano, “Digital Design,” 4th Edition, ISBN: 978-81-317-1450-8, Pearson Education (India), Adapted, 2007 (Adapted to Indian University requirements).

  6. Moris M. Mano, “Digital Design,” 4th Edition, ISBN: 978-81-317-0345-8, Pearson Education (India), Adapted, 2007 (Adapted to JNTUniversity requirements).

  7. Moris M. Mano, “Digital Design,” 4th Edition, ISBN: 978-81-317-0345-6, Pearson Education (India), Adapted, 2007 (Adapted to Anna University requirements).

  8. Moris M. Mano, “Digital Design,” 3rd Edition, ISBN: 978-81-317-0091-4, Pearson Education (India), Adapted, 2006 (Adapted to Indian University requirements).

  9. Moris M. Mano, “Digital Design,” 2rd Edition, ISBN: 978-81-780-8555-5, Pearson Education (India), Adapted, 2006 (Adapted to Indian University requirements).

  10. L. Nashelsky and R. Boylestead, “Electronics Devices & circuits theory,” 10th Edition, ISBN: 978-81-317-2700-3, Pearson Education (India), Adapted, 2009 (Adapted to Indian University requirements).

  11. L. Nashelsky and R. Boylestead, “Electronics Devices & circuits theory,” 9th Edition, ISBN: 978-81-775-8158-4, Pearson Education (India), Adapted, 2007 (Adapted to Indian University requirements).

  12. Bhaskara -“Switching theory and logic design,” ISBN: 978-12-590-0442-1, McGraw-Hill (India), Reviewed, July-2011.

  13. Bhaskara -“VLSI design,” ISBN: NA, McGraw-Hill (India), Reviewed, June-2011.

R&D Projects:

  1. Prepared a proposal to Defence Research and Development Organization (DRDO) of India, Titled “Design and Development of Smart Intelligent Algorithms for Visual Surveillance System in Security Applications” with an estimated cost of Rs. 23.6 lakhs; applying for patent.
  2. Preparing a proposal to Technology Systems Development (TSD-DST) programme, Titled “A Smart, intelligent and Novel Embedded Vehicle Interceptor” with an estimated cost of Rs. 12 lakhs.

Patents:

  1. To be filed; Title: “Design and Development of Smart Intelligent Algorithms for Visual Surveillance System in Security Applications”.

Awards:

  1. Recipient of “Best Research Paper Award” from International Academy of Science, Engineering and Technology in International Journal of Electronics and Communication Engineering (IJECE), ISSN: 2278-991X, Dec-2014. IF-3.329, for the paper titled “Design and Optimization of Reversible carry look ahead Adder Circuit.” ( PhD research outcome).

  1. Recipient of “Best Research Paper Award” from IEEE-International Conference on Engineering and Technology (ICETECH-2015), Mar-2015. IF-3.329, for the paper titled “Design of square spiral Nano-antenna in infra-red region for Solar energy Harvesting,” conducted by Rathinam Institute of Technology, Coimbatore, Tamilnadu, India. IEEE Explorer: 978-1-4799-7678-2/15/$31.00, ©2015 IEEE, (Conference Record Number: #35961), 20th March 2015, pp:1026-1031.

  1. Recipient of “Best Teacher Award” from Carrier Launcher (India), Bangalore, May 2006.

 

Notifications / CIrculars