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Dr. Eleena Mohapatra

 

Assistant Professor
Educational Qualification

B.Tech.- Biju Patnaik University of Technology, Odisha (E&T)

M.Tech – Biju Patnaik University of Technology, Odisha (VLSI & ESD)

Ph.D-Siksha ‘O’ Anusandhan (Deemed to be University), Odisha(Micro Electronics)
Experience

Teaching : 9 years

Research: 3 Years
Area of Intreast

Nanoscale Semiconductor Devices, VLSI Circuits and Devices
Date of joining RVCE  27-10-2022

Number of UG Projects Guided: 01

Publications:

International Journal Publications

  1. J. Jena, D. Jena, E. Mohapatra, et al. FinFET-Based Inverter Design and Optimization at 7 Nm Technology Node. Silicon (2022). DOI: 10.1007/s12633-022-01812-6

  2. E. Mohapatra, T. P. Dash, J. Jena, S. Das, and C. K. Maiti, “Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes,” SN Appl. Sci., vol. 3, no. 5, pp. 1–13, Apr. 2021. DOI: 10.1007/S42452-021-04539-Y.

  3. E. Mohapatra, T. P. Dash, J. Jena, S. Das, and C. K. Maiti, “Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors,” Phys. Scr., vol. 95, no. 6, p. 065808, May 2020. DOI: 10.1088/1402-4896/ab89f5.

  4. E. Mohapatra; T.P. Dash; S. Dey; J. Jena; S. Das; C.K. Maiti , “Vertically-stacked silicon nanosheet field effect transistors at 3 nm technology nodes - simulation at nanoscale” International Journal of Nanoparticles, Vol. 12 No. 3, pp. 224–237, 2020. DOI: 10.1504/IJNP.2020.109546.

  5. E. Mohapatra, R.K. Nanda, S. Das, T.P. Dash J. Jena and C.K. Maiti , “Strain engineering in AlGaN/GaN HEMTs for performance enhancement,” Int. J. Nano Biomater., vol. 9, no. 1/2, p. 34, 2020. DOI: 10.1504/IJNBM.2020.107414.

  6. Eleena Mohapatra, “A Novel Design of QPSK Modulator for High Data Rate Transmission” in International Journal of Computer Applications, vol. 975, pp. 8887, 2014.

  7. T. P. Dash, E. Mohapatra, and C. K. Maiti, “Deformation-induced stress/strain mapping and performance evaluation of a-IGZO thin-film transistors for flexible electronic applications,” J Soc Inf Display., pp.1–13, Aug. 2020. DOI: 10.1002/jsid.963.

  8. T. P. Dash, E. Mohapatra, J. Jena, S. Das, S. Dey, and C. K. Maiti, “Nanosized Metal-Grain-Granularity Induced Characteristics Fluctuation in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node,” International Journal of Nanoscience, 2019. DOI: 10.1142/S0219581X20400050.

  9. T. P. Dash, J. Jena, E. Mohapatra, S. Das, S. Dey, and C. K. Maiti, “Role of stress/strain mapping and random dopant fluctuation in advanced CMOS process technology nodes,” Int. J. Nano Biomater., vol. 9, no. 1/2, p. 18, 2020. DOI: 10.1504/IJNBM.2020.107413.

  10. S. Dey, J. Jena, E. Mohapatra, T. P. Dash, S. Das and C. K. Maiti, “Design and Simulation of Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes,” Physica Scripta, 2019.  IOP Publisher. DOI: 10.1088/1402-4896/ab4621.

  11. J. Jena, T. P. Dash, E. Mohapatra, S. Dey, S. Das, and C. K. Maiti, “Fin Shape Dependence of Electrostatics and Variability in FinFETs,” Journal of Electronic Materials, vol. 48, 2019. DOI: https://doi.org/10.1007/s11664-019-07480-4.

  12. T. P. Dash, J. Jena, E. Mohapatra, S. Dey, S. Das, and C. K. Maiti, “Stress-induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7nm Technology Nodes,” Journal of Electronic Materials, vol. 48, pp.5348-5362, 2019. DOI: 10.1007/s11664-019-07348-7.

  13. S. Das, T.P. Dash, D. Jena, E. Mohapatra, C. K. Maiti, “Strain-Engineering in AlGaN/GaN HEMTs: Impact of Silicon Nitride Passivation Layer on Electrical Performance”, Physica Scripta, vol. 96, pp. 124074, 2021. DOI: 10.1088/1402-4896/ac3ef9.

  14. T. P. Dash, S. Dey, S. Das, E. Mohapatra, J. Jena, and C. K. Maiti, “Strain-Engineering in Nanowire Field-Effect Transistors at 3nm Technology Node,” Phys. E Low-dimensional Syst. Nanostructures, vol 118, p. 113964, April 2020. (Elsevier Publisher, I.F.=3.176, SCI indexed). DOI: 10.1016/j.physe.2020.113964.

  15. S. Das, S. Dey, T.P. Dash, E. Mohapatra, J. Jena and C. K. Maiti, “Impact of NBTI and Hot Carrier Stress on nanowire Characteristics,” Nanomaterials and Energy, vol. 8, pp.1-7, 2019. DOI: 10.1680/jnaen.19.00022.

  16. T. P. Dash, S. Dey, S. Das, J. Jena, E. Mohapatra, and C. K. Maiti, “Performance Comparison of Strained-SiGe and Bulk-Si Channel FinFETs at 7N Technology Node,” Journal of Micromechanics and Microengineering, vol. 29, pp. 104001, 2019. (IOP Publisher, I.F. 2.141, SCI Indexed). DOI: 10.1088/1361-6439/ab31c8.

  17. T. P. Dash, S. Dey, S. Das, J. Jena, E. Mahapatra, and C. K. Maiti, “Source/Drain Stressor Design for Advanced Devices at 7nm Technology Nodes,” Nanoscience & Nanotechnology-Asia, vol. 9, 2019. DOI: 10.2174/2210681209666190809101307.

International Conference Publications

  1. D. Jena, T. Dash, S. Das, E. Mohapatra, J. Jena and S. Choudhury, "Simulation of Recessed Gate Pseudomorphic AlGaAs/InGaAs/GaAs HEMT for RF Applications," 2022 6th International Conference on Devices, Circuits and Systems (ICDCS), 2022, pp. 219-222, DOI: 10.1109/ICDCS54290.2022.9780836.

  2. E. Mohapatra, T. P. Dash, S. Das, J. Jena, J. Nanda and C. K. Maiti, "Investigation of Work Function Variation on the Electrical Performance of sub-7nm GAA FETs," 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 2021, pp. 103-106. DOI: 10.1109/DevIC50843.2021.9455911.

  3. E. Mohapatra, T. P. Dash, J. Jena, S. Das and C. K. Maiti, "Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 331-334. DOI: 10.1109/VLSIDCS47293.2020.9179913.

  4. E. Mohapatra, S. Das, T. P. Dash, S. Dey, J. Jena and C. K. Maiti, "Strain Engineering in AlGaN/GaN HEMTs for Performance Enhancement," 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), IIT Hyderabad, India, 2019, pp. 55-58. DOI: 10.1109/MOS-AK.2019.8902465.

  5. E. Mohapatra, S. Das, T. P. Dash, S. Dey, J. Jena and C. K. Maiti, "High Frequency Performance of AlGaN/GaN HEMTs Fabricated on SiC Substrates," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 326-330. DOI: 10.1109/DEVIC.2019.8783562.

  6. Eleena Mohapatra, “A Novel Design of QPSK Modulator for High Data Rate Transmission” in IEEE Conference on Microelectronics, Circuit and Systems Kolkata July 11-13, 2014.

  7. T. P. Dash, E. Mohapatra, S. Choudhury, B. Jena and C. K. Maiti, "Strained SiGe Channel TFTs For Flexible Electronics Applications," 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 2021, pp. 355-358. DOI: 10.1109/DevIC50843.2021.9455788.

  8. D. Jena, E. Mohapatra, F. A. Ali and T. P. Dash, "A Simulation Study of 2-D Electron Gas in GaN HEMT for High- Speed Applications," 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 2021, pp. 411-415. DOI: 10.1109/DevIC50843.2021.9455878.

  9. S. Das, E. Mohapatra, S. Choudhury, T. P. Dash and C. K. Maiti, "Stress-Engineered AlGaN/GaN High Electron Mobility Transistors Design," 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 2021, pp. 471-473. DOI: 10.1109/DevIC50843.2021.9455852.

  10. S. Dey, E. Mohapatra, J. Jena, S. Das, T.  P. Dash, and C. K. Maiti, “Performance Prediction of Stacked Nanowire Transistors in the Presence of Random Discrete Dopants and Metal Gate Granularity,” in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp.65-69, 2019. DOI: 10.1109/DEVIC.2019.8783687.

  11. S. Dey, T. P. Dash, E. Mohapatra, J. Jena, S. Das and C. K. Maiti, "Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes," IEEE International Conference on Devices for Integrated Circuit (DevIC-2019), Kalyani, India, 2019, pp. 94-98. DOI: 10.1109/DEVIC.2019.8783385.

  12. T. P. Dash, S. Dey, E. Mohapatra, S. Das, J. Jena, and C. K. Maiti, “Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes”, in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp. 99-103, 2019. DOI: 10.1109/DEVIC.2019.8783300.

  13. T. P. Dash, J. Jena, E. Mohapatra, S. Dey, S. Das, and C. K. Maiti, “Role of stress/Strain Mapping in Advanced CMOS Process Technology Nodes,” in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp. 21-25, 2019. DOI: 10.1109/DEVIC.2019.8783211. 

  14. S. Dey, T. P. Dash, E. Mohapatra, J. Jena, S. Das, and C. K. Maiti, “Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes,” in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp. 65-69, 2019. DOI: 10.1109/DEVIC.2019.8783385.

  15. T. P. Dash, S. Das, S. Dey, E. Mohapatra, J. Jena, and C. K. Maiti, “SPICE Parameter Extraction of Tri-Gate FinFETs- An Integrated Approach,” in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp. 291-294,2019. DOI: 10.1109/DEVIC.2019.8783725.

  16. S. Das, T. P. Dash, S. Dey, E. Mohapatra, J. R. Jena, and C. K. Maiti, “NBTI Degradation and Recovery in Nanowire FETs,” in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp. 70-74, 2019. DOI: 10.1109/DEVIC.2019.8783566.

  17. S. Dey, J. Jena, T. P. Dash, E. Mohapatra, S. Das and C. K. Maiti, “Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering,” 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), Hyderabad, India, 2019, pp. 29-33. DOI: 10.1109/MOS-AK.2019.8902440.

  18. T. P. Dash, S. Dey, J. Jena, S. Das, E. Mohapatra, and C. K. Maiti, “Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node,” in IEEE International Conference on Device Integrated Circuits (DevIC-2019), pp. 286-290, 2019. DOI: 10.1109/DEVIC.2019.8783717 

  19. T. P. Dash, S. Dey, S. Das, E. Mohapatra, J. Jena, and C. K. Maiti, “Stress analysis in uniaxially strained SiGe channel FinFETs at 7N technology Nodes” 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp. 171-175, 2018. DOI: 10.1109/EDKCON.2018.8770446.

  20. T. P. Dash, S. Dey, S. Das, E. Mohapatra, J. Jena, and C. K. Maiti, “Stress Tuning in NanoScale FinFETs at 7nm” 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp. 166-170, 2018. DOI: 10.1109/EDKCON.2018.8770517.

  21. S. Dey, T. P. Dash, S. Das, E. Mohapatra, J. Jena, and C. K. Maiti, “Gate-All-Around Si-Nanowire Transistors: Simulation at Nanoscale,” 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp. 137-141, 2018. DOI: 10.1109/EDKCON.2018.8770471 

  22. S. Dey, T. P. Dash, S. Das, J. Jena, E. Mohapatra, and C. K. Maiti, “Variability Due to Orientation Dependent Oxide Thickness in SOI-FinFETs,” 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp. 152-156, 2018. DOI: 10.1109/EDKCON.2018.8770390.

Books/ Chapters Contributed

  1. Eleena Mohapatra, “Nanosheet Transistors” In: Fabless Semiconductor Manufacturing- In the Era of Internet of Things, Chinmay K. Maiti (ed), pp. 165-209, New York, Jenny Stanford Publishing, 2023.

  2. E. Mohapatra, T.P. Dash, J. Jena, S. Das, J. Nanda, C.K. Maiti (2020) Performance Analysis of Si-Channel Nanosheet FETs with Strained SiGe Source/Drain Stressors. In: G. Pradhan, S. Morris, N. Nayak (eds) Advances in Electrical Control and Signal Systems, Lecture Notes in Electrical Engineering, vol. 665, pp 329-337, Springer, Singapore. DOI: 10.1007/978-981-15-5262-523.

  3. T. P. Dash, E. Mohapatra, S. Das, S. Choudhury, and C. K. Maiti, “Toward Ultimate Scaling: From FinFETs to Nanosheet Transistors,” Lect. Notes Networks Syst., vol. 151, pp. 225–232, 2021. DOI: 10.1007/978-981-15-8218-9_19.

  4. R.K. Nanda, E. Mohapatra, T. P. Dash, P. Saxena, P. Srivastava, R. Trigutnayat, C. K. Maiti (2020) Atomistic Level Process to Device Simulation of GaNFET Using TNL TCAD Tools. In: Pradhan G., Morris S., Nayak N. (eds) Advances in Electrical Control and Signal Systems, Lecture Notes in Electrical Engineering, vol 665. pp 815-826, Springer, Singapore. DOI: 10.1007/978-981-15-5262-561.

  5. J. Jena, T.P. Dash, E. Mohapatra, S. Das, J. Nanda, C.K. Maiti (2020) Modeling and Performance Analysis of n-FinFETs: A Comparative Study. In: Pradhan G., Morris S., Nayak N. (eds) Advances in Electrical Control and Signal Systems, Lecture Notes in Electrical Engineering, vol 665. pp 765-776 Springer, Singapore. DOI: 10.1007/978-981-15-5262-5_57

Membership of Bodies:

Member IEEE (Membership Id: 95192648)

Member IETE (Associate Member (Lifetime))

Notifications / CIrculars