Date of Joining at RVCE : 29 August 2012
Subjects Handled : Analog microelectronics circuits, Mixed mode VLSI design, Analog integrated circuits design, Basic Electronics, Digital VLSI Design
No. of Projects guided to UG Students : 9
No. of Projects guided to PG Students : 4
Publication Details
Journals:
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Chinmaye Ramamurthy, P. Surya, Chetan D Parikh and Subhajit sen “A DE-
TERMINISTIC DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADCS USING A NON-NESTED ALGORITHM”, Analog Integrated Circuits and Signal Processing volume 110, Pp 557–568, 2022.
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Chinmaye Ramamurthy, Chetan D Parikh and Subhajit sen “DETERMIN- ISTIC DIGITAL CALIBRATION TECHNIQUE FOR 1.5 BITS/STAGE PIPELINED AND ALGORITHMIC ADCS WITH FINITE OP-AMP GAIN AND LARGE CAPACITANCE MISMATCHES”, Circuits, Systems and Signal processing, 40(8), Springer-2021.
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Chinmaye R, Vishwas venkatesh “A COMPARATIVE STUDY OF SRAM CELLS”, International journal of innovative research in Electrical, Electronics, Instrumentation and Control Engineering, Vol 3, Issue 11, Nov 2015.
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Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches Journal Circuits, Systems, and Signal Processing, 40(8), 3684-3702 DOI 10.1007/s00034-021-01652-6
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Ravish Aradhya H V, Chinmaye R, Muralidhara K N, "Design, Optimization and Synthesis of efficient Reversible Logic Binary Decoder", International Journal for computer applications, Vol. 46, No. 6, pp. 45-51, May 2012.
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Chinmaye R, Harish K “Design and Optimization of Asynchronous counter using Reversible logic”, International Journal of Engineering Research and Technology, Vol 4, Issue.06, June 15
International Conferences:
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Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by direct extraction of Calibration Coefficients, VLSID,2021
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Ravish Aradhya H V, Chinmaye R, Muralidhara K N, "Design, Optimization and Synthesis of efficient Reversible Logic Binary Encoder", International Conference on Recent Trends and Computer Science Engineering, Apollo College of Engineering, Chennai, pp. 187, May 3-4th 2012.
National conferences:
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Ravish Aradhya H V, Chinmaye Ramamurthy, Muralidhara K N, "Design and Optimization of Reversible Logic Decoder for Low Power Applications", National Conference on Advanced VLSI Design Embedded Technology, Northern India Engineering College, Delhi, pp. 67, Feb 28-29th 2012.
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Chinmaye R, Harish K “Design, Optimization and application of Flip Flop using Reversible Logic”, Research Challenges in Power, Control, Communication and Instrumentation leading to Sustainable Technologies, Apr 15
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