Date of Joining at RVCE :20/10/2013

Subjects Handled : CMOS VLSI Design, Low Power VLSI Design, Digital Design Using HDL,Analog Microelectronic Circuits, Analog Integrated Circuit Design, Analysis and Design of Digital Circuits, Elements of Electronics Engineering

No. of Projects guided to UG Students : 20

No. of Projects guided to PG Students :08

Publication Details

International Journals:

1. Arunkumar P Chavan.et.al “Ultra Low Power Hybrid Voltage Controlled Oscillator for Data Acquisition System” International Journal of Emerging Trends & Technology in Computer Science Vol 11 issue 4, 2022.

2. Arunkumar P Chavan, Dr Ravish Aradhya “Design and Analysis of Low Power VCO Enabled quantizer for CT Sigma Delta ADC” Indian Journal of Public Health Research and Development, Vol: 10 Issue:5 2019.

3. Arunkumar P Chavan, Dr B V Uma “An Electronic Smart Jacket for the Navigation of Visually Impaired Society” Materials today proceedings Volume 5, Issue 4, Part 3, 2018.

4. Arunkumar P Chavan “VLSI Implementation of Split-radix FFT for High Speed Applications” International Journal of Computer Applications (0975 – 8887) Volume 157 – No 7, January 2017.

5. Arunkumar P Chavan.et.al “Design and Implementation of 64-bit Vedic Multiplier for Digital Signal Processing (DSP) Application” International Vedic and Mathematics New Delhi 2017.

6. Arunkumar P Chavan .et.al “Design and Implementation of 8-Bit ALU based on Sub-threshold Adiabatic Logic (SAL)” Communications on Applied Electronics (CAE) – ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA. 2017

7. Arunkumar P Chavan .et.al “High Speed 32-bit Vedic Multiplier for DSP Applications” International Journal of Computer Applications (0975 – 8887) Volume 135 – No.7, February 2016.

8. Arunkumar P Chavan .et.al “A 1.5V 3bit, 500MS/s LOW POWER CMOS Flash ADC” International Journal Of Engineering And Computer Science March 2014.

9. Arunkumar P Chavan.et.al “A 1.5-V, 10-bit, 200-MS/s CMOS Pipeline Analog-toDigital Converter” International Journal of Computer Applications 2014.

10. Arunkumar P Chavan.et.al “A NOVEL DESIGN OF 9-BIT PIPELINE ADC” International Journal of Scientific & Engineering Research, Volume 5, Issue 10, October-2014.

11. Arunkumar P Chavan .et.al “A 9-bit, 200MS/s Low power CMOS pipeline ADC” International Journal of Engineering and Technology 2014.

12. Arunkumar P Chavan.et.al “An Efficient Design of 3bit and 4bit Flash ADC” International Journal of Computer Applications January 2013.

13. Arunkumar P Chavn.et.al “Bio-Inspired Motion Detector Model Simulated on Xilinx ISE” International Journal of Computer Applications (0975 – 8887) May 2013.

14. Arunkumar P Chavan .e.al “Improved Fault Tolerant Sparse KOGGE Stone ADDER” International Journal of Computer Applications (0975 – 8887) Volume 75– No.10, August 2013.

15. Arunkumar P Chavan.et.al “Design of a 1.5-V, 4-bit Flash ADC using 90nm Technology” International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, December 2012.

International Conferences:

1. Arunkumar P Chavan.et.al “Design of Low Power and Energy Efficient 5 X 5 Multipliers” IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014.

2. Arunkumar P Chavan.et.al “An Electronic Smart Jacket for the Navigation of Visually Impaired Society” ILAFM 2017.

3. Arunkumar P Chavan “Sub threshold Adiabatic Logic (SAL) based building blocks for Combinational system design” 2nd IEEE International Conference On Recent Trends in Electronics Information & Communication Technology (RTEICT), May 19-20, 2017, India

4. Arunkumar P Chavan.et.al “Design and implementation of 16 tap FIR filter for DSP Applications” Second International Conference on Advances in Electronics, Computer and Communications (ICAECC-2018).

5. Arunkumar P Chavan.et.al “Design of Magnetic Tunnel Junction Based Low Power Non-Volatile Ternary Content Addressable Memory” 4th International Conference on Recent Trends On Electronics, Information, Communication & Technology pp-1309-1315 2019.

6. Arunkumar P Chavan.et.al “Design and Verification of ECC Scheme To Optimize Area and Tester Time in OTP Rom Controller” 4th International Conference on Recent Trends On Electronics, Information, Communication & Technology pp-1309-1315 2019.

7. Arunkumar P Chavan.et.al “Design of Area Efficient Multiply Accumulator Unit in Quantum Dot Cellular Automata (QCA)” Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems Springer Publisher, 2020.

8. Arunkumar P Chavan.et.al “Design of High Performance & Low-Power H-Tree Using Multi Threshold Split-Io Buffers” 2020 International Conference on Smart Electronics and Communication (ICOSEC) volume 1 2020.

9. Arunkumar P Chavan.et.al “Design and Synthesis Of Low Power, High Speed 5th Order Digital Decimation Filter For Sigma- Delta Analog To Digital Converter” International Conference On Communication And Signal Processing (ICCSP) pp 0092-0096, 2020.

10. Arunkumar P Chavan.et.al “Design of Low Power & High Performance Multi Source H-Tree Clock distribution network” IEEE VLSI Device Circuit and System (VLSI DCS) 2020 pp-0084-0087, 2020.

11. Arunkumar P Chavan.et.al “A 2.5 mw Low-Power Dual VCO Quantizer For∑-∆ Modulator In 0.09nm CMOS” IEEE VLSI Device Circuit and System (VLSI DCS) PP- 479-483 2020.

12. Arunkumar P Chavan.et.al “Ultra-Low Power, Area Efficient and High-Speed Voltage Level Shifter Based on Wilson Current Mirror” 2021 IEEE Mysore Sub Section International Conference (MYSURUCON), volume 1, PP 107-113, 2021.

13. Arunkumar P Chavan.et.al “Ultra Design and Optimization of Timing Errors on Swapping of Threshold Voltage” 2021 IEEE Mysore Sub Section International Conference (MYSURUCON), volume 1, PP 687-691, 2021.

14. Arunkumar P Chavan.et.al “Integration and Verification of Ip Cores on Soc” 2021 IEEE Mysore Sub Section International Conference (MYSURUCON), volume 1, PP 120-125, 2021.

15. Arunkumar P Chavan.et.al “Design and Implementation of Automated Industrial Robots in Cylinder Liner Production Lines” Asian Conference on Innovation in Technology (ASIANCON), volume 2 pp- 1-7, 2021.

16. Arunkumar P Chavan.et.al “IOT Enabled Real- Time Availability and Condition Monitoring of CNC Machines” IEEE International Conference on Internet of Things and Intelligence System (IOTAIS) volume1 pp 78-84 2021.

National Conferences:

1. Arunkumar P Chavan.et.al “An optimized design and verification methodology using modified layer test bench approach” Conference on knowledge dissemination of PG project and research works-2018

2. Arunkumar P Chavan.et.al “Design and verification of reconfigurable memory” Conference on knowledge dissemination of PG project and research works-2018

3. Arunkumar P Chavan.et.al “Design and analysis component for the enabled quantizer ring different stages of ring oscillator in CT SD ADC” Conference on knowledge dissemination of PG project and research works-2018.

4. Arunkumar P Chavan.et.al “Development of mpvic in UVM” national conference on research challenge in power, communication and instrumentation leading to sustainability RVCE April 2015.

5. Arunkumar P Chavan .et.al “Estimation of Nitrogen in leaves using Image processing ” NCSEM oxford college of engineering 26th- 27th MAY, 2017.

Consultancy:

1. “Process Monitoring using IOT funded by Kennametal” India Limited , Tumkur Road Bengaluru.

Awards:

1. Best Paper Award for the titled “Ultra Low Power Area Efficient and High Speed Voltage Level Shifter based On Wilson Current Mirror” organized by IEEE Mysurucon-2021.

2. Best Young Teacher Award for the academic year 2021-2022 under ISTE –RVCE CHAPTER.

3. Best paper Award for the title “Verification IP development for AMBA ACE Protocol using UVM” organized by Microelectronics, computing systems, machine learning & Internet of things (MCMI-2022).