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Mrs. Namita Palecha

Assistant Professor

Educational Qualification

B.E.(Electronics and Communication),

M.Tech.(VLSI Design & Microelectronics),

(Ph.D)

Experience

Teaching: 15 years

Industry : NIL

Area of Interest

VLSI Circuits Testing and Testability

Email ID

namitapalecha@rvce.edu.in

 

 

Date of Joining at RVCE : 10th July 2007

Subjects Handled :

Analysis and Design of Analog circuits, Basic Electronics, HDL, VLSI Circuits, Analog & Mixed mode VLSI Design, VLSI Design, CMOS VLSI Design, Testing and testability for digital circuits, Analysis and Design of Digital Circuits.

No. of Projects guided to UG Students : 30

No. of Projects guided to PG Students : 24

Publication Detail

1.International Journals:

  1. Rakshak Udupa TS, Shashank K Holla, Namita Palecha "Design of a Start-Up Sequence Controller for a Mammography Machine"Journal of University of Shanghai for Science and Technology Volume 23, Issue 6, June - 2021 , pp 537-545, ISSN: 1007-6735

  2. TR Nischith, J Alwyn, N Palecha "Novel Approach to Measure Internal Power Domain PG Route Weakness "Journal of University of Shanghai for Science and Technology Volume 23, Issue 6, June - 2021 , pp 704-708, ISSN: 1007-6735

  3. Suraj B Ghale, Namita P, Design " Implementation of Memory BIST for Hybrid Cache Architecture", 6th International Conference on Communication and Electronics Systems (ICCES 2021), IEEE XPLORE ISBN 978-0-7381-1405-7

  4. Mahesh Bhat K, Namita Palecha, "Implementation of a Parallel Fault Simulation System using PODEM in a Hardware Accelerator using Python", Journal of University of Shanghai for Science and Technology, Volume 23, Issue 6, June -2021, ISSN: 1007-6735

  5. Namita Palecha, Natraj, Prateek, Rajiv Mittal,Suma M S “Programmable-FSM Based Low Power MBIST “ in Journal of Emerging Technologies and Innovative Research, , Volume 5, Issue 12, December 2018, ISSN-2349-5162.

  6. Kiran K P , Namita P, Siva SankarA,”An efficient approach for Boundary scan verification for system on chip”, International Journals of Advance Research, volume 3, issue 7, July 2015, ISSN 2320-5407 .

2. International Conferences:

  1. AS Mangawati, N Palecha,"Clock Gating Integration Using 18T-TSPC Clocked Flip Flop"2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT)

  2. N Sameeksha Rai, Namita Palecha, Mahesh Nagarai"A brief overview of Test Solution Development for Semiconductor Testing"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)

  3. Natraj, Prateek, Rajiv Mittal, Namita Palecha, Suma M S” Programmable FSM Based Built-In-Self-Test For Memory” , IEEE International Conference on Recent Trends In Electronics, Information & Communication Technology-2016, ISBN: 978-1-5090-0774-5

  4. P Gujamagadi, PR Sankolli, P Kumar, R Nayak, N Palecha, MS Suma “Design of high speed vedic multiplier for high fault coverage and comparative analysis with conventional multiplier” at IEEE IACC-2015 , ISBN: 978-1-4799-8047-5, pp 738-742.

  5. Suma M.S, Namita Palecha , K.S.Gurumurthy “Register Transfer Level Fault Modeling in Verilog Environment” 4th International conference on Electronics & Computer Technology-ICECT ,ISSN 978-1-4673-1850-1/12,pp-610-613.

  6. M. Poornima, M.S.Suma, Namita Palecha, T. Malavika “Fault-Tolerant Reversible Logic For Combinational Circuits: A Survey” International Conference on VCASAN Lecture Notes in Electrical Engineering 258, DOI: 10.1007/978-81-322-1524-0_12, pp.79-86.

  7. Namita Palecha M Poornima ,MS Suma “Fault Modeling for Register Transfer Level” poster paper ,proc of Int.Conf.on Advances in Signal Processing and Communication, DOI: 03.LSCS.2013.3.17,pp80-83

 

 

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