Educational Qualification
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B.E / B.Tech.(Electronics & Communication),
M.E/M.Tech.(Digital Electronics),
Ph.D (Image Processing)
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Date of Joining at RVCE : 22-09-2015
Subjects Handled : Digital Electronics, Analog circuits, Image Processing, Linear Integrated Circuits, Field Theory, Control Systems.Digital system design using Verilog HDL
Number of UG Projects Guided: 10
Publication Details
Journals:
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Nagaraj Bhat et al "Performance analysis of machine learning algorithm of detection and classification of brain tumor using computer vision" Advances in Engineering Software,elsevier (Q1 Journal) 2022.
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Nagaraj Bhat, U Eranna "Pattern Approximation Based Generalized Image Noise Reduction Using Adaptive Feedforward Neural Network"International Journal of Electrical and Computer Engineering,vol.8,2018(Q2 Journal)
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Nagaraj Bhat, U Eranna "Complementary Approach for Image Edge Detection Using Rough Mirror Mapping in Neural Network"nternational Journal of Engineering & Technology,vol.7,isuue3.4, pp.127-132,2018.
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Facial Expression Recognition using FLD combined with PCA is published in IJARECE-2012 volume 2 issue 1.
International Conferences:
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Nagaraj Bhat, U Eranna "Robust Global Gradient Thresholds Estimation in Anisotropic Diffusion for Image Restoration Using DE"International Conference on Next Generation Computing Technologies,677-691,Springer, Singapore.
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Nagaraj Bhat, Roshni Sen "An Overview of Near Field Communication and its Application in the Payment Sector" Journal of University of Shanghai for Science and Technology,2021
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Nagaraj Bhat , Santosh Herur "Analysis and design of 1GHz PLL for fast phase and frequency lock"Proc. of Int. Conf. on Recent Trends in Signal Processing, Image Processing and VLSI
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BM Mahendra, Savita Sonoli, Nagaraj Bhat, T Raghu "IoT based sensor enabled smart car parking for advanced driver assistance system"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)
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Participated and Presented paper on “Facial Expression Recognition” in ICRTCSE-2012 held on May 3rd & 4th in Appolo Engineering college ,Chennai.
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Participated and Presented paper on Analysis and Design of 1GHz PLL for Fast Phase and Frequency Lock in ICRTCSV-2014 held at DBIT Bangalore.
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